The present invention relates to the field of electronic circuit technology; specifically it relates to a phase lock loop (PLL) circuit.
A phase-locked loop (PLL) is a control system that generates an output signal whose phase is related to the phase of an input signal. In a simplified version, a PLL can be viewed as an electronic circuit having a variable frequency oscillator and a phase detector. The oscillator generates a periodic signal, and the phase detector compares the phase of that signal with the phase of an input periodic signal and adjusts the oscillator to keep the phases matched. A feedback loop is used to couple the output signal back to the input signal for comparison.
In addition to synchronizing signals, a phase-locked loop can track an input frequency, and it can generate a frequency that is a multiple of the input frequency. These properties are used for computer clock synchronization, demodulation, and frequency synthesis, etc. For example, phase-locked loops are widely employed in radio, telecommunications, computers, and other electronic applications. They can be used to demodulate a signal, recover a signal from a noisy communication channel, generate a stable frequency at multiples of an input frequency (frequency synthesis), or distribute precisely timed clock pulses in digital logic circuits such as microprocessors. Since a single integrated circuit can provide a complete phase-locked-loop building block, the technique is widely used in modern electronic devices.
A charge pump is an important component in a PLL. The charge pump provides a high loop gain of the circuit, so that when the PLL is phase locked, the phase difference between the input and the output of the frequency divider is zero. It can reduce the variation of control signals in the voltage-controlled oscillator (VCO) and reduce output spurs (Spur). However, conventional charge pumps suffer from many limitations, as will be described below.